1. Field of the Invention
This invention relates generally to an addressing scheme for multiple microelectronic components. More particularly, the invention relates to a self-addressing scheme for stackable microelectronic components, such as memory chips. Even more particularly, this invention relates to a self-addressing scheme for stackable microelectronic components used for cardiac stimulators.
2. Description of the Related Art
With the advent of the transistor a few decades ago and the ensuing developments in integrated circuit technology, electronic circuits have become smaller and smaller. Because the size of the circuits has decreased, the functionality of an electronic circuit of any given size has tended to increase dramatically. The microprocessor is largely responsible for this dramatic increase in functionality, so it is no surprise that many of today""s electronic circuits operate under microprocessor control. As is well known, microprocessors are essentially generic devices that may be programmed to perform a wide variety of functions. These specific functions are dictated by software programs that control the microprocessor, and these programs are stored in memory devices that are coupled to the microprocessor.
Like microprocessors, the memory devices accessed by microprocessors are integrated circuit devices. In other words, the memory devices include semiconductor chips that contain the memory circuit. Most integrated circuit chips, including memory chips, are mounted in a package. Most commonly, a plurality of pins are coupled to the integrated circuit chip, and plastic is molded over the chip to encase it while allowing the pins to extend from the plastic. Although such packages occupy a substantially greater area that the integrated circuit chip itself, most applications are not so size sensitive that the increased expense of customized alternatives is a viable option.
However, certain electronic products do benefit from minimized packaging. For instance, in the field of cardiac stimulators, benefits are derived from minimizing the size of the cardiac stimulator, while maximizing its functionality and longevity. As most people are aware, cardiac stimulators are medical devices that have been developed to facilitate heart function. For instance, if a person""s heart does not beat properly, a cardiac stimulator may be used to provide relief. The cardiac stimulator delivers electrical stimulation to a patient""s heart using a pulse generator for creating electrical stimulation pulses and a conductive lead for delivering these electrical stimulation pulses to the designated portion of the heart.
The electronic circuitry for generating the pulses is typically contained within a case. The proximal end of the conductive lead is coupled to the case, while the distal end of the conductive lead is coupled to the heart. Although the distal end of the lead is always internal to the patient""s body, the case may be internally implanted or carried external to the patient""s body. When an internally mounted case is used, the case is implanted underneath the patient""s skin or musculature. Conversely, when an externally mounted case is used, the proximal end of the conductive lead passes through an opening in the patient""s chest wall to couple to the externally mounted case. A variety of situations exist where externally mounted cases are preferable for a particular patient, but internally mounted cases are generally preferred.
Implantable cases are generally disk-like in shape. This shape facilitates the implantation of the case underneath a patient""s skin or musculature. Advantageously, this shape also tends to minimize patient discomfort and to limit the size of the bulge created by the implanted device. Of course, it is also desirable to limit the size of the case for these same reasons.
Because the functionality of cardiac stimulators continues to increase in order to enhance the performance of the cardiac stimulator and, thus, the patient""s well-being, the memory requirements of implantable cardiac stimulators have tended to increase. However, due to the size requirements discussed above, electronic circuitry contained in the cases of most implantable cardiac stimulators is already quite densely packed. Current implantable cardiac stimulators contain their main memory on a single chip. For instance, pacemakers typically include a random access memory on the microprocessor chip having a memory array of about 1 k bits by 8 bits, and defibiltators typically include a random access memory chip external to the microprocessor chip having a memory array that may be as large as 128 k bits by 8 bits (most of which is dedicated to storing diagnostic data and digitized waveforms). Thus, only a limited amount of memory exists to accommodate the various different functions that designers may wish to program into the cardiac stimulator. As a result, designers must, at times, make difficult decisions regarding the functions that an implantable cardiac stimulator possesses, as well as the manner in which it performs these functions. Also, as memory arrays grow in size, yield typically decreases, thus increasing the cost of the memory compared to the same amount of memory in smaller arrays.
The present invention may address one or more of the problems set forth above.
In accordance with one aspect of the present invention, there is provided a semiconductor memory. The memory includes a plurality of memory chips that are stacked one on top of another. Each of the plurality of memory chips has a memory array and a plurality of address lines. The plurality of address lines of each of the plurality of memory chips are coupled together. Each of the plurality of memory chips also includes an addressing circuit. Each addressing circuit is adapted to receive address signals on at least one of the plurality of address lines. Each addressing circuit enables its respective memory chip in response to a given address signal received on the at least one of the plurality of address lines.
In accordance with another aspect of the present invention, there is provided a semiconductor memory. The memory includes a plurality of memory chips that are stacked one on top of another. Each of the plurality of memory chips has a memory array and a plurality of address lines. The plurality of address lines terminate in a plurality of bonding pads. The plurality of bonding pads corresponding to similar address lines on each of the plurality of memory chips are aligned with one another. The plurality of bonding wires are coupled to the respective plurality of bonding pads to couple the plurality of address lines of each of the plurality of memory chips together. The plurality of bonding wires extend generally parallel to one another. Each of the plurality of memory chips also includes an addressing circuit. Each addressing circuit is adapted to receive address signals on at least one of the plurality of address lines. Each addressing circuit enables its respective memory chip in response to a given address signal received on the at least one of the plurality of address lines.
In accordance with still another aspect of the present invention, there is provided a semiconductor memory. The memory includes a memory chip that has a memory array, an addressing circuit, and a plurality of address lines. At least one of the plurality of address lines is coupled to the addressing circuit. The addressing circuit is programmable to enable and disable the memory chip in response to a given address signal received on the at least one of the plurality of address lines.
In accordance with yet another aspect of the present invention, there is provided a semiconductor memory. The memory includes a memory chip that has an array of memory locations, an addressing circuit, and a plurality of address lines. A first portion of the plurality of address lines are sufficient to address all of the memory locations in the array, and a second portion of the plurality of address lines are coupled to the addressing circuit. The addressing circuit enables the memory chip in response to a given address signal received on the second portion of address lines.
In accordance with a further aspect of the present invention, there is provided a semiconductor memory. The memory includes a memory chip that has a memory array having 2N addressable locations, an addressing circuit, and N+X address lines, where X is at least one. The X address lines are coupled to the addressing circuit. The addressing circuit is programmable to enable and disable the memory chip in response to a given address signal received on the X address lines.
In accordance with an even further aspect of the present invention, there is provided an electronic device. The device includes a microprocessor and a stack of memory chips. Each of the memory chips has an array of memory locations and an addressing circuit. A plurality of address lines are coupled to each of the memory chips and to the microprocessor. A first portion of the plurality of address lines are sufficient to address all of the memory locations in any one of the arrays, and a second portion of the plurality of address lines are sufficient to select one of the memory chips. The addressing circuit of each of the memory chips is coupled to the second portion of the plurality of address lines. One of the addressing circuits enables its respective memory chip in response to a given address signal received on the second portion of address lines.
In accordance with a still further aspect of the present invention, there is provided a cardiac stimulator. The cardiac stimulator includes a case and pulse generation circuitry contained in the case. The pulse generation circuitry includes a stack of memory chips. Each of the memory chips has an array of memory locations and an addressing circuit. A plurality of address lines is coupled to each of the memory chips. A first portion of the plurality of address lines is sufficient to address all of the memory locations in any one of the arrays, and a second portion of the plurality of address lines is sufficient to select one of the memory chips. The addressing circuits of each of the memory chips is coupled to the second portion of the plurality of address lines. One of the addressing circuits enables its respective memory chip in response to a given address signal received on the second portion of address lines. A conductive lead is adapted to couple the pulse generation circuitry to myocardial tissue.
In accordance with a yet further aspect of the present invention, there is provided a cardiac stimulator. The cardiac stimulator includes a case. Pulse generation circuitry is contained in the case. The pulse generation circuitry includes a stack of addressable memory chips. A conductive lead is adapted to couple the pulse generation circuitry to myocardial tissue.